Physical Coding Sublayer

1 Description
2 Physical Coding Sublayer (PCS) specifications
- 2.1 10 Gigabit Ethernet
- 2.2 Lattice Semiconductor multi-protocol
3 References
4 External links

Description

The Physical Coding Sublayer (PCS) further helps to define physical layer specifications(speed and Duplex modes etc..) for networking protocols like Fast Ethernet, Gigabit Ethernet and 10 Gigabit Ethernet.

The Ethernet PCS sublayer is part of the Ethernet PHY layer. The hierarchy is as follows:

Data Link Layer (Layer 2)
- LLC (Logical Link Control Sublayer)
- MAC (Media Access Control Sublayer)
  - RS (Reconciliation Sublayer) - This sublayer processes PHY Local/Remote Fault messages and handles DDR conversion
PHY Layer (Layer 1)
- PCS (Physical Coding Sublayer) - This sublayer performs autonegotiation and coding such as 8b/10b encoding
- PMA (Physical Medium Attachment Sublayer) - This sublayer performs PMA framing, octet synchronization/detection, and $x^7%2Bx^6%2B1$ scrambling/descrambling
- PMD (Physical Medium Dependent Sublayer) - This sublayer consists of a transceiver for the physical medium

Physical Coding Sublayer (PCS) specifications

10 Gigabit Ethernet

10GBASE-R (LAN) is the serial encoded PCS that allows for Ethernet framing at a rate of approximately 10.3 Gbit/s (MAC= 10,000 Gbit/s, overhead= 64 B/66 B effective rate= 10,000 * 66/64= 10,312.5 - see also 64b/66b encoding). This rate does not match the rate 9.953 Gbit/s used in SONET and SDH and is not supported over a WAN based on SONET or SDH.

10GBASE-X (LAN) uses similar coding methods as 10GBASE-R but is only used in the definition of 10GBASE-LX4. This is mainly because LX4 operates on both single and multimode fibers, giving it a unique set of specifications as defined in its PMD.

10GBASE-W (WAN) defines WAN encoding for 10GbE, it encodes the frames so that they are compatible with SONET STS-192c data rates and SDH VC-4-64 transmission standards allowing for 10 Gbit/s transmission across a WAN. It does this by wrapping the 64/66b payload into a SONET frame, making the effective rate 9.95 Gbit/s.

Lattice Semiconductor multi-protocol

"PCS logic can be configured to support numerous industry-standard, high-speed serial data transfer protocols.""LatticeECP3 SERDES/PCS Usage Guide". Lattice semiconductor Corporation: p 8–1. http://www.latticesemi.com/documents/tn1176.pdf.

References

Barbieri, Alessandro. "10 GbE and Its X Factors". Packet: Cisco Systems Users Magazine 17 (3): 25–28. http://www.cisco.com/asiapac/campaigns/metroethernet/files/10ge_po_pack_mag_arti.pdf. Retrieved 2007-12-31.